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[VHDL-FPGA-Verilog] profiles

Description: source code of counter,ram,lfsr etc
Platform: | Size: 2048 | Author: narsimha | Hits:

[VHDL-FPGA-Verilog] ram_Test

Description: RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
Platform: | Size: 3072 | Author: 王欢 | Hits:

[VHDL-FPGA-Verilog] ram2

Description: RAm的 verilog描述，在Quartus中验证正确，可根据程序改成其他参数-Verilog description of RAm in Quartus verify correct procedures can be changed in accordance with other parameters
Platform: | Size: 2048 | Author: fang | Hits:

[Software Engineering] planta_fagner

Description: is a test of a verilog implementation to do a oscilloscope with dual-port RAM
Platform: | Size: 88064 | Author: felipellbb | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-Verilog] ug_ram

Description: RAM design for FPGA in verilog
Platform: | Size: 289792 | Author: NguyenViet | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[VHDL-FPGA-Verilog] CODE

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram verilog
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[VHDL-FPGA-Verilog] RAM

Description:
Platform: | Size: 573440 | Author: luoxs | Hits:

[VHDL-FPGA-Verilog] spmem.tar

Description: Sinlge port RAM VHDL/Verilog design
Platform: | Size: 1024 | Author: Ravi | Hits:

[VHDL-FPGA-Verilog] ram_dp_sr_sw

Description: dual ram port in verilog
Platform: | Size: 1024 | Author: sayhaa | Hits:

[VHDL-FPGA-Verilog] ram-rom-VerilogHDL

Description: 利用Verilog编写的各种RAM ROM的代码以及他们的测试模块-Prepared using a variety of RAM ROM Verilog code and their test module
Platform: | Size: 5120 | Author: 王体奎 | Hits:

[VHDL-FPGA-Verilog] Single-port-RAM-

Description: 单口RAM带CLR信号的verilog程序。很详细的.-Single-port RAM with a CLR signal
Platform: | Size: 1118208 | Author: 赵峰 | Hits:

[VHDL-FPGA-Verilog] AHB_slave-ram

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram under the verilog code
Platform: | Size: 1024 | Author: 吴亮 | Hits:

[VHDL-FPGA-Verilog] RAM_BLOCK

Description: Ram block code in Verilog
Platform: | Size: 25600 | Author: M. Usman | Hits:

[VHDL-FPGA-Verilog] 一种arm7源码（Verilog）

Description: 一种arm7源码（verilog），arm7结构比较老了，不过用来初学还是不错的(A kind of ARM7 source code (Verilog))
Platform: | Size: 61440 | Author: kody.he | Hits:

[VHDL-FPGA-Verilog] basic verilog codes

Description: Basic Verilog code includes RING and Johnson counters, Up-down counters, RAM, ROM, SIPO, PISO, SISO, PIPO, Mealy and Moore FSM codes
Platform: | Size: 9386 | Author: spgp1306 | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:

[VHDL-FPGA-Verilog] verilog实例 [43项]

Description: 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
Platform: | Size: 190464 | Author: hayto | Hits:
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